High performance semiconductors devices are often packaged in expensive ceramic or metal packages for enhanced electrical performance, at least during the initial stages of product introduction. However as the selling price of the device is driven down, the use of such packages by a semiconductor manufacturer becomes cost ineffective. One of the most common approaches to alleviating packaging costs of high performance devices is to use a plastic package. However, high performance devices have a relatively large pin-count which is not easy to accommodate in a plastic package using conventional single layer leadframes. Use of single layer leadframes in high pin-count devices creates high inductance levels between leads, resulting in undesirable signal noise during simultaneous signal switching. Furthermore, in order to handle the large currents used in high performance devices, a single layer leadframe requires a larger number of power and ground leads, and thus a larger number of power and ground pads on a die, to distribute the additional current. Increasing the number of leads and number of pads contradicts a goal of semiconductor manufacturers which is to minimize device size.
Some semiconductor manufacturers have been able to produce relatively low-cost plastic packages for high performance devices which overcome the above disadvantages by utilizing multilayer leadframes. Conventional multilayer leadframes typically include either a power or a ground voltage plane on which a semiconductor die is mounted. The voltage plane is usually formed from conventional leadframe materials, such as copper, a copper alloy, or a nickel-iron alloy, and is attached to a more or less standard single layer leadframe. Attachment of the voltage plane to a single layer leadframe is often accomplished by using a non-conductive adhesive tape, but may also be done by welding a portion of the plane to one or more leads of the leadframe. While a multilayer leadframe having a full voltage plane is an improvement over conventional single layer leadframes in terms of electrical performance, a disadvantage with such leadframes is that a manufacturer is limited to having either a power plane or a ground plane, but not both.
Another known semiconductor device having a multilayer leadframe combines a first full voltage plane with a second partial voltage plane to improve electrical performance over the one-plane multilayer leadframe design discussed above. In the device, a full voltage plane is attached to a single layer leadframe in a manner similar to that described above. In addition, an annular voltage plane is attached to the top of the full voltage plane, for instance by a non-conductive adhesive tape. A semiconductor die is positioned in the central opening of the annular plane and is attached to the full plane. Power bond pads of the die are wire bonded to one of either the annular plane or the full plane, while ground pads are wire bonded to the remaining voltage plane. A semiconductor device utilizing a multilayer leadframe with one full voltage plane and one partial voltage plane has improved electrical performance over a device having only a single voltage plane. However, a semiconductor manufacturer sacrifices electrical performance because either a power plane or a ground plane is limited in area due to the annular shape of one of the voltage planes.